Bus design can be classified into interleaved bus design and non-interleaved bus design based on address decoding. An overwhelming majority of existing bus design is based on the non-interleaved bus design. The interleaved bus design is being increasingly adopted to enable software to use a storage resource more flexibly. An interleaved bus can implement a pipelined operation for block data access operations sent by each master device, and can make full use of bandwidths of a whole system. However, if a master device sends discrete single operations, the pipelined operation cannot be implemented normally, bandwidth utilization efficiency of the interleaved bus is reduced significantly, and in a worst case, efficiency drops to 1/M (M is the number of master interfaces of the bus) of original efficiency.